The present invention relates to a data processor for processing data transferred from a system bus and a data transfer method employed by the data processor.
FIG. 20 is a block diagram of a conventional data processor. The data processor of FIG. 20 is a drawing processor including a host CPU 91 for control of the entire drawing apparatus, a main memory 92 used by the host CPU 91, a drawing processing unit 93, a drawing memory 94 and a main bus 95.
The drawing processing unit 93 includes a CPU interface 96 functioning as the interface with the host CPU 91, a data processing section 97, and a drawing memory interface 98 functioning as the interface with the drawing memory 94. The data processing section 97 performs issuance of an interrupt request to the host CPU 91 and the like when data processing under control of the host CPU 91 via the CPU interface 96 and supply of data to be processed are necessary and in other occasions. The drawing memory 94 includes a drawing command region and a frame region, and stores drawing data in the drawing command region and drawing-processed data in the frame region. The main bus 95 connects the host CPU 91, the main memory 92 and the drawing processing unit 93 with one another.
In the conventional data processor described above, supply of data to the drawing processing unit 93 is totally performed under control of the host CPU 91. To state specifically, when supply of data is necessary, the drawing processing unit 93 sends an interrupt signal IS to the host CPU 91 to request an interrupt. Receiving the interrupt, the host CPU 91 supplies data to the drawing processing unit 93 to be stored in the drawing memory.
In general, for reduction in power consumption, supply of a clock signal is partly halted depending on the operation mode of an apparatus, and power supply is turned off depending on the operation mode. Also, as disclosed in Japanese Laid-Open Patent Publication No. 9-319453, for example, the following measures are taken to reduce power consumption. A processor or the like halts supply of a clock signal or power to an unused operator according to an instruction, or supplies a clock signal or power only to a portion of a register or an operator related to eight lower-order bits, for example, depending on the bit length of an instruction.
However, when a drawing apparatus as shown in FIG. 20 is used to construct a system such as a car navigation system, the performance of the CPU is lost by frequent occurrence of data transfer, resulting in deterioration in the performance as the system. To suppress the deterioration in performance, the capacities of the drawing memory and the main memory may be increased. However, this disadvantageously increases the cost.
A digital signal processor (DSP), an application-specific integrated circuit (ASIC) and the like are controlled under instructions from the host CPU controlling these devices. Therefore, when reduction in power consumption is intended for the DSP, ASIC and the like, only macro control is permitted in which processing is halted from start to end in a certain internal operator while processing is performed from start to end in another internal operator. For this reason, delicate power control to an internal block level is not possible when different internal parts operate with different processing data items.
An object of the present invention is providing a data processor capable of lightening the load of a host CPU during data transfer.
Another object of the present invention is providing a data processor with reduced power consumption.
According to the present invention, the data processor, which is controlled by an external bus master such as a host CPU, includes a control register for holding information such as an address at which data to be processed is stored and the number of words to be transferred, so that the data processor itself can serve as a bus master to perform data transfer to an operation memory without putting a load on the external bus master.
To state specifically, the present invention is directed to a data processor for processing operation data stored in a memory connected to an external bus in the order of operations, including: an interface section for holding a parameter required for transfer of the operation data; an operation section receiving the operation data from the interface section for performing predetermined processing; and an operation memory for storing the operation data transferred, wherein the interface section sequentially transfers the operation data from the memory connected to the external bus to the operation memory using the parameter, and sequentially transfers the operation data from the operation memory to the operation section.
With the above configuration, the data processor itself transfers operation data according to the parameter held by the control register, to acquire the data. This lightens the load related to data transfer processing on the external bus master such as a host CPU.
In the data processor described above, preferably, the interface section transfers transfer information for transfer of operation data to be next processed to the operation memory, together with the operation data, and when reading the transfer information from the operation memory, the interface section sequentially transfers the operation data corresponding to the transfer information from the memory connected to the external bus to the operation memory.
With the above configuration, the data processor can read transfer information for transfer of operation data to be processed next, and thus the data processor itself can start DMA transfer and acquire the operation data. This prevents the external bus master controlling the external bus from being loaded with parameter setting when parameters for DMA transfer must be set repeatedly, for example, when an operation data group must be divided for transfer because the capacity of the operation memory is limited, and when operation data groups must be sequentially generated and transferred to the data processing section.
Preferably, the data processor described above further includes a data transfer management section for holding information indicating whether or not the interface section is under transfer of the operation data.
With the above configuration, the data processor is provided with the data transfer management section that makes a notification of completion of DMA transfer instructed from the external bus master. This makes it possible to overwrite a region of the memory connected to the external bus from which data has already been read, and thus eliminates the necessity of unduly increasing the capacity of the memory connected to the external bus. The cost of the data processor can therefore be reduced.
In the data processor described above, preferably, the interface section notifies an external bus master controlling the external bus of termination of transfer of the operation data by generating an interrupt.
With the above configuration, the data processor itself can notify the external bus master of the status of data transfer. Therefore, the external bus master can timely know the timings of preparation of data required for the next operation, transfer of the data to the memory connected to the external bus, and the like.
In the data processor described above, preferably, the interface section includes a data transfer wait register holding information set by the external bus master controlling the external bus when start of transfer of the operation data is newly required, and halts the current transfer of the operation data according to the information held by the data transfer wait register.
With the above configuration, in occurrence of sudden data change, the interface section can halt currently-running DMA transfer and start new transfer.
In the data processor described above, preferably, the operation section includes a plurality of circuits for processing commands included in the operation data, and the interface section supplies a clock signal to a circuit among the plurality of circuits that processes a command included in the operation data transferred to the operation section according to a control field of the command.
With the above configuration, a portion of the operation section required for the next processing is known prior to transfer of data for the processing to the operation section. Therefore, the clock signal can be supplied under control only to the portion of which activation is actually required. Thus, reduction in power consumption is possible.
Preferably, the interface section starts supply of the clock signal according to a first control field located at the head of the command, and halts the supply of the clock signal according to a second control field located at the end of the command.
With the above configuration, supply of the clock can be started before start of a command and halted after the processing of the command.
Preferably, the circuit of the operation section receiving the clock signal outputs a done signal indicating termination of the processing of the transferred command to the interface section, and the interface section starts supply of the clock signal according to a control field located at the head of the command, and halts the supply of the clock signal to the circuit that has outputted the done signal upon receipt of the done signal.
With the above configuration, each circuit of the operation section itself halts supply of the clock signal after termination of processing. Therefore, the interface section is relieved of timing control for halting the clock signal.